Making multilayer 3d capacitors using arrays of upstanding rods or ridges

ABSTRACT

In one embodiment, a method for making a 3D Metal-Insulator-Metal (MIM) capacitor includes providing a substrate having a surface, forming an array of upstanding rods or ridges on the surface, depositing a first layer of an electroconductor on the surface and the array of rods or ridges, coating the first electroconductive layer with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer. In some embodiments, the array of rods or ridges can be made of a photoresist material, and in others, can comprise bonded wires.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a division of U.S. patent application Ser. No. 14/304,535, filed Jun. 13, 2014, incorporated herein by reference.

BACKGROUND

1. Field of the Invention

This disclosure generally relates to methods for making integrated circuit components, and more particularly, to making three-dimensional (3D), metal-insulator-metal (MIM) capacitors upon or within associated substrates.

2. Related Art

MIM capacitors can be provided on semiconductor chips having active circuit elements, i.e., “active chips,” or on passive chips containing passive circuit elements, such as capacitors, inductors, resistors, etc., for subsequent mounting to active chips.

Conventional capacitors made in, e.g., a silicon substrate, can be of two general types. A first type can be used, e.g., to store charge for each bit in a dynamic random access (DRAM) chip. A second type can be used for “decoupling” applications, wherein the primary focus has been on “planar” or so-called “two-dimensional” (2D) capacitors made on or in passive substrates and having very thin alternating dielectric and electroconductive layers, in single or multi-layer formats. Both types of capacitors can have limitations, e.g., low capacitance densities and low quality factors (i.e., efficiencies).

Methods for making capacitors in “blind” or “through” vias or trenches in substrates that overcome some of these drawbacks of the prior art are described in commonly owned U.S. Pat. No. 8,502,340 to V. Oganesian et al., the entire disclosure of which is incorporated herein by reference. These “three-dimensional” (3D) “via” or “trench” capacitors can achieve higher capacitances due to the relatively larger surface areas of their sidewalls, but can be difficult to coat with metal/dielectric layers with uniformly conformal coverage due primarily to limited mass transport into trenches or vias that are relatively deep and/or narrow.

Accordingly, a need exists for methods for making capacitors on or in associated substrates that achieve substantially higher capacitances than conventional 2D capacitors, but within which the MIM layers are substantially easier to form than in conventional via- or trench-type capacitors.

SUMMARY

In accordance with the present invention, novel methods are provided for making high-capacitance, 3D, multilayer or Metal-Insulator-Metal (MIM) capacitors on or in an associated substrate that overcome the above and other drawbacks of the prior art.

In one embodiment, a method for making a MIM capacitor comprises providing a substrate having a surface, forming an array of upstanding rods or ridges on the surface, depositing a first layer of an electroconductor on the surface and the array of rods or ridges, coating the first electroconductive layer with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer. In some embodiments, the array of rods or ridges can comprise a photoresist material, and in others, multiple alternating electroconductive and dielectric layers can be formed.

In another embodiment, a method for making a capacitor comprises providing a substrate having a surface, depositing a first layer of an electroconductor on the surface, bonding an end of at least one upstanding metal wire to the first electroconductive layer, coating the first electroconductive layer and the at least one metal wire with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer.

In yet another embodiment, the associated substrate can include a cavity, and the array of upstanding rods or ridges, and hence, the capacitor, can be formed such that it is disposed partially or completely within the cavity.

The scope of this invention is defined by the claims appended hereafter, which are incorporated into this section by reference. A more complete understanding of the features and advantages of the novel 3D MIM capacitors and the methods for making them will be afforded to those skilled in the art by a consideration of the detailed description of some example embodiments thereof presented below, especially if such consideration is made in conjunction with the appended drawings briefly described below, in which like reference numerals are used to identify like elements illustrated in one or more of the respective figures thereof.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1A is a vertical cross-sectional view of a portion of a substrate containing a blind via or trench capacitor;

FIGS. 1B and 1C are top plan views of the substrate portion of FIG. 1A, wherein the capacitor therein is respectively shown as a via-type capacitor or a trench-type capacitor;

FIG. 2A is a vertical cross-sectional view of a portion of a substrate having an array of upstanding rods or ridges disposed thereon in accordance with an example embodiment of the present invention;

FIGS. 2B-2D are top plan views of the substrate portion of FIG. 2A, wherein the array disposed there is respectively shown as comprising an array of ridges, each having a generally rectangular cross-section, an array of rods, each having a generally square or rectangular cross-section, or an array of wires, having a generally round cross-section;

FIGS. 3A-3F are vertical cross-sectional views of a portion of a substrate respectively illustrating sequential steps of an example embodiment of a method for making a multilayer, 3D capacitor on a surface of the substrate in accordance with the present invention;

FIGS. 3G and 3H are vertical cross-sectional views of the substrate portion of FIGS. 3A-3F illustrating the capacitor made therein respectively disposed on a surface of the substrate or on the floor of a cavity in the substrate;

FIG. 4A is a vertical cross-sectional view of the substrate and capacitor of FIG. 3G, showing the capacitor housed within a cavity of a second substrate such as a handle wafer;

FIG. 4B is a vertical cross-sectional view of the substrate and capacitor of FIG. 3H, showing the capacitor disposed on the floor of the cavity of the substrate and covered over by a second substrate, such as a handle wafer;

FIG. 5A is a vertical cross-sectional view of the substrate and capacitor of FIG. 4A, showing the capacitor housed within a cavity of a second substrate and disposed adjacent to a pair of semiconductor packages;

FIG. 5B is a vertical cross-sectional view of the substrate and capacitor of FIG. 3H, showing the capacitor disposed on the floor of the cavity of the substrate and adjacent to a pair of semiconductor packages;

FIGS. 6A and 6B are vertical cross-sectional views of a portion of a substrate having an array of upstanding rods or ridges disposed thereon and illustrating the formation thereon of a self-assembled monolayer (SAM) of a dielectric comprising an alkanethiol having a thiol disposed at opposite ends thereof; and,

FIGS. 7A-7D are molecular diagrams of four different alkanethiols useful for forming dielectric SAMs in accordance with the present invention.

DETAILED DESCRIPTION

This disclosure presents example embodiments of high-capacitance, multilayer, 3D MIM capacitors that are formed on or in an associated substrate, together with some example methods for making them.

FIG. 1A is a vertical cross-sectional view of a portion of a substrate 10 containing a “blind” via or trench capacitor 12 of a type disclosed in U.S. Pat. No. 8,502,340 referenced above. As illustrated in FIG. 1A, the substrate 10 itself includes generally planar, parallel upper and lower surfaces 14 and 16, and can be comprised of a semiconductor, such as silicon, glass, ceramic, polytetrafluoroethylene (PTFE), a polymer, such as a polyimide or an epoxy (which can be reinforced with, e.g., glass or other fibers), or a rigid or flexible “interposer” of a known type that can include a redistribution layer (RDL). As illustrated in the embodiments of FIGS. 5A and 5B, the RDL 136 can comprise a plurality of electroconductive pads and traces and used for the redistribution of electrical signals within the substrate 10 and/or their conveyance to its lower surface 16, and can be disposed on one, the other, or both of the upper and lower surfaces 14, 16 of the substrate 10, or alternatively or additionally, partially or completely disposed within its thickness.

In the particular example embodiment illustrated in FIGS. 1A-1C, the capacitor 12 comprises a “blind” via-type MIM capacitor (as seen in FIG. 1B), or alternatively, a blind trench-type MIM capacitor (as seen in FIG. 1C), depending on whether the recess 18 within which the capacitor 12 is formed is generally round in cross-section, as illustrated in the top plan view of FIG. 1B, or horizontally elongated, as illustrated in the top plan view of FIG. 1C. Thus, in FIG. 1B, the width L1 of the recess 18 is about equal to its height L2, whereas, in FIG. 1C, the width. L1 of the recess 18 is substantially greater than its height L2. Further, the recess 18 is referred to as a “blind” via or trench because the feature does not extend entirely through the thickness of the substrate 10. However, as described in the above-referenced patent, it is also possible to make “through” via- or trench-type capacitors 12 that extend through the entire thickness of the substrate 10.

Also, as can be seen in the particular example capacitor 12 of FIG. 1A, the side wall 20 of the recess 18 is tapered or flared inwardly with depth, which in the case of the via-type capacitor 12, gives the recess 18 a frusto-conical shape. However, as known to those of some skill in, e.g., the etching art, it is also possible to make recesses 18 that have substantially vertical side walls, or alternatively, that flare outwardly with depth, depending on the particular application at hand.

The capacitor 12 is referred to as a MIM capacitor because it includes at least one layer of an Insulator 22, or dielectric, sandwiched between at least two electroconductive, e.g., Metal, layers 24, which serve as the plates of the capacitor 12. As a practical matter, the number of alternating Insulator and Metal layers 22 and 24 that can be incorporated into the capacitor 12 to increase its capacitance is limited by the space available within the recess 18, i.e., width and/or depth, and the ability to coat its interior surfaces uniformly with the respective materials of the alternating layers. The particular example capacitor 12 illustrated in FIG. 1A includes four dielectric layers 22 and four electroconductive layers 24, but as indicated above, that number can vary.

A first one of the dielectric layers 22 serves to insulate a first one of the electroconductive layers 24 from the side wall 20 of the recess 18, and each of the three remaining dielectric layers 22 are respectively sandwiched between first and second, second and third, and third and fourth ones of the electroconductive layers 24. As illustrated in the particular embodiment of FIG. 1A, the first and third electroconductive layers 24 are tied together at the upper surface 14 of the substrate 10 in a first electroconductive pad 26 so as to define one “plate” and an interconnected “electrode” of the capacitor 12, whereas, the second and fourth electroconductive layers 24 are tied together at the opposite side of the upper surface 14 of the substrate 10 in a second electroconductive pad 28 so as to define the second plate and interconnected electrode of the capacitor 12. The remaining volume within the recess 18 can be filled with a dielectric “filler” material 30, e.g., epoxy, that serves to insulate and protect the fourth or innermost electroconductive layer 24 from ambient influences.

As discussed above, the 3D via or trench capacitor 12 fabricated in the thickness of the substrate 10 achieves an advantage over a conventional planar 2D capacitor formed on or in the substrate 10 by including a third dimension, viz., height, in the computation of the area of the MIM layers of the capacitor. Thus, 2D capacitors have a capacitance that is a function of their planar length times their planar width. All other factors remaining the same, the capacitance of 3D capacitors such as the above is a function of their planar length times their planar width times their vertical height, as measured in the direction of the thickness of the substrate 10. That is, the tapered side wall(s) 24 of the recess 18 upon which the MIM layers 22 and 24 are disposed serve to substantially increase the area of the layers 22, 24, and hence, the capacitance of such devices, relative to those of conventional 2D capacitors.

While 3D via or trench capacitors can achieve higher capacitances due to the relatively larger surface areas of their side walls, in some instances in which the vias or trenches are especially narrow and/or deep, their walls can be difficult to coat with uniform or conformal coats of the metal/dielectric layers due to limited mass transport into the depths of the narrow/deep vias or trenches. A need therefore exists for methods for making 3D multilayer MIM capacitors on or in associated substrates that achieve substantially higher capacitances than conventional 2D capacitors, but within which conformal MIM layers are easier to create than in conventional via- or trench-type capacitors. Following is a description of some example embodiments of such capacitors, along with some example methods and materials for making them, in which the “negative” features, i.e., the vias or trenches upon which the alternating dielectric and electroconductive layers are deposited, are “reversed,” or transformed into “positive,” upstanding features that are substantially easier to coat with such layers.

FIG. 2A is a vertical cross-sectional view of a portion of a substrate 100 having an array 102 of upstanding structures, viz., “rods” or “ridges” 104, disposed thereon in accordance with an example embodiment of the present invention, and FIGS. 2B-2C are alternative top plan views of the substrate portion of FIG. 2A, wherein the array 102 is respectively shown as comprising an array of upstanding ridges 104 (FIG. 2B), each having a generally rectangular horizontal cross-section, an array of upstanding rods 104 (FIG. 2C), each having a generally square or rectangular horizontal cross-section, or an array of upstanding wires (FIG. 2D), each having a generally circular horizontal cross-section, such as might be present in a “wire bond” embodiment described in more detail below. The array 102 forms the foundation of a multilayer, 3D, MIM capacitor 124 (see FIGS. 3F-3H) that is constructed on the array 104 in the manner described below using well-known photolithography and integrated circuit (IC) fabrication techniques and apparatus.

As in the via or trench capacitor example above, the substrate 100 can include generally parallel and planar upper and lower surfaces 106 and 108 and can comprise a relatively wide variety of materials, e.g., a semiconductor, such as silicon, glass, ceramic, polytetrafluoroethylene (PTFE), a polymer, such as a polyimide or an epoxy (which may or may not be reinforced with, e.g., glass or other fibers), or a rigid or flexible interposer which might or might not include an RDL.

As those of some skill will understand, the primary function of the upstanding structures 104 of the array 102 is to increase the height, i.e., the vertical or Z dimension, and hence, the area of the MIM layers of the capacitor 124 formed thereon, without increasing its “footprint,” i.e., its horizontal X and Y dimensions, on the surface 106 of the substrate 100. In this regard, in the particular example embodiment of FIGS. 2A-2D, the array 100 is illustrated as being a square or rectangular array. However, it should be understood that the array 100 can take other shapes, e.g., circular, elliptical, polygonal, and the like, depending on the particular application at hand. Similarly, while the horizontal cross-sectional shapes of the rods or ridges 104 are illustrated as being square, rectangular, or circular, these shapes can also be easily varied, again depending on the problem being addressed.

Additionally, it is desirable in general to maximize both the number of the features 104 and their “aspect ratio” (AR), defined herein as the height or Z dimension of the feature 104 divided by the smaller of its horizontal or X/Y dimensions, and hence, the surface area, of the upstanding rods or ridges 104, but consistent with their retaining adequate columnar stability. It has been discovered that rods or ridges 104 comprising a photoresist material can be made reliably with a smaller cross-sectional dimension of about 5 μm (5×10⁻⁶ meters) and with a vertical dimension or height of between about 100 μm and 500 μm, i.e., with an AR of between about 20 to 1 and 100 to 1, and that they can disposed at a pitch of about 10 μm, i.e., with a spacing of about 5 μm between adjacent rods or ridges 104, to form an array 102.

A similar situation obtains in a “wire bond” arrangement, i.e., one in which the rods 104 of the array 102 can comprise conventional bonded metal wires of a type used to interconnect stacked or so-called “Package-on-Package” (PoP) integrated circuit (IC) packages in which a “Bond Via Array” (BVA), i.e., an array of relatively stiff, upstanding bonded metal wires, each having a lower end bonded to a surface of a substrate and a free-standing opposite upper end, is used to electroconductively interconnect a first IC package stacked on top of a second IC package. Examples of such BVAs can be found in, e.g., commonly owned U.S. Pat. No. 8,404,520 to E. Chau et al.; and U.S. Pat. Pub. Nos. 2013/0313716 A1 by I. Mohammed, 2014/0036454 A1 by T. Caskey et al., and 2013/0200533 by E. Chau et al., the entire disclosure of each of which is incorporated herein by reference.

Using such BVA techniques, arrays 102 can be confected that comprise generally cylindrical wire-bonding wires, each having a diameter of about 50 μm and a vertical dimension or height of about 500 μm, i.e., an AR of about 10 to 1, and that are disposed at a pitch of about 200-240 μm, i.e., with a spacing of 150-190 μm between adjacent wires, with repeatable reliability. The wires 104 can comprise, for example, gold (Au), copper (Cu) or aluminum (Al), can have other cross-sectional shapes, e.g., polygonal, and can be coated or plated with another metal, such as palladium (Pd), which has a higher modulus of elasticity than the foregoing “core” materials and thereby renders them stiffer in the vertical direction.

FIGS. 3A-3F are vertical cross-sectional views of the substrate 100 respectively illustrating sequential steps of an example embodiment of a method for making a capacitor on the surface 106 of the substrate 100 in accordance with the present invention. As illustrated in FIG. 3A, the first step of the method involves forming an array 104 comprising at least one rod or ridge 104 on the upper surface 106 of the substrate 100. In one “photoresist” embodiment, this comprises coating the surface of the substrate with a photoresist material, e.g., by spin coating, photopatterning the photoresist to define the at least one upstanding rod or ridge 104 therein, and stripping the excess photoresist from the surface 106 of the substrate 100 so as to leave the at least one rod or ridge 106 upstanding thereon. Thus, in FIG. 3A, the array 102 can comprise a plurality of rods or ridges 104 made of a photoresist material and having, for example, the number and shape of the upstanding features 104 illustrated in the top plan views of FIGS. 2B-2D. The photoresist material can comprise, for example, Benzocyclobutene (BCB), polyimide, spun-on glass, or SU-8, all of which are dielectrics.

Accordingly, as illustrated in FIG. 3B, the next step of the method comprises depositing a first layer 110 of an electroconductor, e.g., a metal, on the surfaces 106 of the substrate 100 and the at least one rod or ridge 104 to at least partially define one of the plates of the capacitor 124. The layer 110 of electroconductor can comprise, for example, Tantalum (Ta), Copper (Cu), Titanium (Ti), Titanium Nitride (TiN), Silver (Ag), Gold (Au), or Palladium (Pd), and can be deposited using a variety of known techniques, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD) or sputtering. As those of some skill in this art will understand, the deposition of the first and subsequent layers of electroconductive and dielectric materials into the open space above the array 102 of rods or ridges 104 is relatively free of limits on mass transport, compared to that in the example via or trench capacitor described above.

As illustrated in FIG. 3C, the first electroconductive layer 110 is then conformally coated with a thin but uniform first layer 112 of a dielectric. In this regard, it is desirable that the dielectric material have a relatively high dielectric constant, k. Suitable dielectric materials that can be coated on the electroconductor layer 110 using, for example, ALD, CVD or sputtering, include hafnium oxide (HfO2) (k=25), tantalum pentoxide (Ta2O5) (k=22), zirconium dioxide (ZrO2) (k=25), yttrium oxide (Y2O3) (k=15), lanthanum oxide (La2O3) (k=30), titanium dioxide (TiO2) (k=80), strontium titanate (SrTiO3) (k=2,000), or Parylene (k≈3), which can be vapor phase deposited on the first electroconductive layer 110.

As illustrated in FIGS. 6A and 6B, in another embodiment, the first dielectric layer 112 can comprise a “self-assembled monolayer” (SAM) 114 comprising molecules 116 containing at least one thiol group, and preferably, alkanethiol molecules 116 having a thiol group at both ends thereof, such as illustrated in the molecular diagrams of FIGS. 7A-7D. These compounds can include, for example, molecules of Dithiothreitol (C4H10S2), 1,2-Ethanedithiol (C2H4(SH)2), Biphenyl-4,4′-dithiol (HSC6H4SH), or 1,4-Benzenedimethanethiol (C6H4(CH2SH)2).

Self-assembly is a process in which a disordered system, typically a liquid solution of molecules, forms an organized structure or pattern, in this case, an extremely thin but uniform, defect-free “monolayer” on the electroconductive layers of the capacitor, as a consequence of specific, local interactions among the components themselves, without any external direction. Discussions of such self-assembled monolayers and techniques for making them can be found in, e.g., “Self-assembled Monolayers of Thiols and Dithiols on Gold,” Chem. Soc. Rev., 2010, 39, 1805-1834, and “Self-Assembled Monolayers of and Multilayers of Conjugated Thiols, a,o-Dithiols, and Thioacetyl-Containing Adsorbates. Understanding Attachments between Potential Molecular Wires and Gold Surfaces,” J. Am. Chem. Soc., 1995, 117, 9529-9534, the teachings of which are incorporated herein by reference. Use of these techniques enable the formation of a uniform, defect-free and “super-thin” dielectric layers, which can be used for any of the dielectric layers described herein and which can result in capacitors exhibiting ultra-high capacitances.

As illustrated in FIGS. 3D-3F, the first dielectric layer 112 is followed by the deposition of alternating electroconductive and dielectric layers over the array 102 until the desired number of alternating layers of the resulting capacitor 124 has been reached. In the particular embodiment illustrated in FIG. 3F, the capacitor 124 includes two dielectric layers 112, 120, and three electroconductive layers 110, 118 and 122, wherein the first dielectric layer 112 is sandwiched between the first and second electroconductive layers 110 and 118, and the second dielectric layer 120 is sandwiched between the second and third electroconductive layers 118 and 122. As discussed above, within practical limits, the number of alternating dielectric and electroconductive layers formed in the capacitor can vary widely.

As discussed above in connection with the via- and trench-type capacitors, it is desirable to create leads or electrodes respectively coupled to the two “plates” of the capacitor 124 for electroconductively interconnecting it with other circuit elements. In the particular example embodiment illustrated in FIGS. 3G and 3H, one of the contacting electrodes 126 of the capacitor 124 is electroconductively coupled to the second electroconductive layer 118, or a first “plate,” of the capacitor 124, and the other electrode 126 is electroconductively coupled to the first and third electroconductive layers 110, 122, or second plate, of the capacitor 124. In only one of many possible embodiments, the electrodes 126 illustrated can be made by depositing a dielectric material 128, such as BCB, polyimide, spin-on glass or SU8, on the upper surface 106 of the substrate in the region where the electrodes 126 are to be formed, and then photopatterning the dielectric material, etching an opening through it down to the electroconductive layer(s) to which the electrodes 126 are to be respectively connected, and then depositing a metal in the openings to define the electrodes 126 and electroconductively couple them to the corresponding electroconductive layers. Of course, other methods of locating, forming and coupling electrodes to the plates of the capacitor can also be used.

A method for making a capacitor 124 on the substrate 100 using the BVA techniques discussed above in which the array 102 comprises one or more upstanding bonded metal wires 104, each having a lower end bonded to a surface of a substrate and a free-standing opposite upper end, is substantially similar to that described above in connection with FIGS. 3A-3H and the photoresist structures, but with the following notable difference.

In order to bond the lower ends of the wires 104 to the upper surface 106 of the substrate 100 using, e.g., a molten “ball”-type bond or an ultrasonic “stitch” or “wedge” type bond, it is desirable to first coat the upper surface 106 of the substrate 100 in the area where the array 102, and hence, the capacitor 124, are to be formed with a metal that is compatible with the metal of the wire bonds, e.g., an alloy of Au, Cu or Al, so that the wires can be reliably bonded to that surface. Further, since both the wires 104 and the metallized area of the substrate surface to which they are bonded are metal, i.e., electroconductive, this is sufficient to define one of the electroconductive layers, e.g., 110 of the capacitor 124 being constructed without the necessity of depositing another electroconductive layer upon them, and such that the next step in the construction of the capacitor 124 after the definition of the array 102 can commence with the coating of the surface 106 and upstanding wires 104 with a dielectric layer. After that, the steps of the method are substantially the same as in the photoresist array 102 method described above.

Comparison of Capacitance of 2D and 3D Capacitors

For illustration purposes, the following is a comparison of the respective capacitances of an example 3D capacitor 124 made in accordance with the methods of the present invention and a 2D capacitor having the same length, width, thickness and number of alternating dielectric and electroconductive layers. In the example 3D capacitor, the array 102 is assumed to be made of SU8 photoresist, to be 1 mm (1×10⁻³ meters) square, and to comprise 10,000 upstanding cylindrical rods 104, each having a diameter of 5 μm, a height of 100 μm, and a center-to-center pitch of 10 μm.

The dielectric layers of both the 2D and 3D capacitors is assumed to have a thickness of 5 nm (5×10⁻⁹ meters) and a dielectric constant k=25 (e.g., HfO₂), the electroconductive layers of both capacitors is assumed to be the same metal and thickness, and it is assumed that there are two alternating dielectric and electroconductive layers in both capacitors.

For the planar or conventional 2D capacitor, the capacitance=8.85×10⁻¹² Farads/meter (F/m)×25×1 mm²/5 nm=44.25 nF.

For the 3D capacitor in accordance with the present invention, the capacitance=2×8.85×10⁻¹² F/m×25×(1 mm²+10,000×3.14×0.005×1 mm²)/5 nm=1.48 μF.

Thus, the 3D capacitor in accordance with the present invention has about 33 times the capacitance of the conventional planar or 2D capacitor, i.e., 1.48 μF/mm² vs. 44.25 nF/mm² for the latter, yet occupies the same 2D space on or in the associated substrate as the latter. As further illustrated in FIGS. 3G and 3H, the capacitor 124 can be formed on the upper surface 106 of the associated substrate 100 (FIG. 3G), or alternatively, on the floor of a cavity 130 in the substrate 100 (FIG. 3H), such that the capacitor 124 is disposed partially or entirely within the cavity 130. As illustrated in FIG. 4A, it is possible to house a capacitor 124 made on the upper surface 106 of the substrate 100 within a cavity 132 that is contained in a second substrate 134, such as a “handle wafer” that is subsequently bonded to the substrate 100 in, e.g., a metal-to-metal or adhesive bond 136.

As illustrated in FIG. 4B, if the capacitor 124 is contained entirely within a cavity 130 of the associated substrate 100, the capacitor 124 can be covered over with a second substrate 134, e.g., a handle wafer, without a corresponding cavity. Alternatively, the cavity 130 can be filled with an insulator, such as an epoxy resin, to protect and seal the capacitor 124 against, e.g., moisture. In either case, and whether a second wafer 134 is used or not, the space immediately above and surrounding the capacitor 124 can be overmolded with, e.g., a protective epoxy shell (not illustrated), to protect and insulate the exterior surface of the capacitor 124. Further, it might be desirable in such cases to modify the electrodes 126 such that their outer ends are exposed at a surface, e.g., of the lower surface, of the protective shell for convenient interconnect access, e.g., with an RDL 136, such as is illustrated in FIGS. 5A and 5B.

As discussed above in connection with FIGS. 4A and 4B, the capacitor 124 can be housed within a cavity 132 of a handle or a cover wafer 134, or alternatively, within a cavity 130 in the substrate 100, and in either case, the substrate 100 can comprise a redistribution layer (RDL) 136 comprising a plurality of electroconductive pads and interconnecting traces useful for, among others, electroconductively connecting the capacitor 124 to other components mounted on, e.g., the same or another substrate, and/or to solder bumps 137, used to electroconductively couple the substrate 100 to an associated printed circuit board (PCB—not illustrated). For example, as illustrated in FIGS. 5A and 5B, the cavities 130, 132 can also be used to house associated integrated (IC) circuit packages 138 and 140, as described in, e.g., commonly owned U.S. patent application Ser. No. 14/214,365 by H. Shen et al., filed Mar. 14, 2014, Ser. No. 14/288,064 by R. Katkar et al., filed May 27, 2014, and Ser. No. 14/268,899 by L. Wang et al., filed May 2, 2014, the entire disclosure of each of which is incorporated herein by reference.

In the particular example embodiments of FIGS. 5A and 5B, the IC packages comprise a single “flip chip” package 138 disposed adjacent to and interconnected with the capacitor 124 and a second package 140 that comprises a pair of interconnected packages stacked on top of one another, which in turn, are connected to the IC package 128 or other components through the RDL 136. The stacked package 140 could comprise, for example, a “package-on-package” (PoP) embodiment of the types described in commonly owned U.S. Pat. Pubs. 2013/0200533 A1 by E. Chau et al., filed Mar. 12, 2013, 2014, 2014/0036454 A1 by T. Caskey et al., filed Mar. 12, 2013, and U.S. Pat. No. 8,404,520 B1 to E. Chau et al., issued Mar. 26, 2013, the entire disclosure of each of which is incorporated herein by reference. The capacitor 124 could function, for example, as a decoupling capacitor connected between the power and ground terminals of the IC 138 to filter out power supply noise or to provide a charge reservoir for power consumption variations and reduce parasitic inductances. However, as those of some skill will understand, the type, number and function of IC packages disposed within the cavities 130, 142 along with the capacitor 124 can vary, depending on the particular application at hand.

As further illustrated in FIGS. 5A and 5B and discussed above, in some embodiments, it can be desirable to fill the empty spaces within the cavities 130, 132 with an appropriate filler 142, such as an epoxy or a thermal interface material, to reinforce the mounting of the capacitor 124 and the IC packages 138, 140 and/or to provide an enhanced heat transfer path between the dies to the surrounding ambient. As illustrated in FIGS. 5A and 5B, in one possible embodiment, this can be effected by forming one or more channels 144 in the handle wafer 134 that communicate between the cavities 130, 132 and an exterior surface of the handle wafer 134, e.g., the upper surface thereof, and then injecting the filler 142 into the cavities through the channels 144.

From the foregoing description, it will by now be clear to those of some skill in this art that many modifications, substitutions and variations can be made in and to the materials and configurations of the high-capacity, multilayer MIM capacitors of the present invention, together with the methods for forming them on or within a cavity of an associated substrate, and in light thereof, that the scope of the present disclosure should not be limited to that of the particular embodiments illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents. 

What is claimed is:
 1. A method for making a capacitor, the method comprising: providing a substrate having a surface; forming at least one upstanding rod or ridge on the surface; depositing a first layer of an electroconductor on the surface and on the at least one rod or ridge; coating the first electroconductive layer with a layer of a dielectric; and depositing a second layer of an electroconductor on the dielectric layer.
 2. The method of claim 1, further comprising coupling each of a pair of electroconductive electrodes to corresponding ones of the first and second electroconductive layers.
 3. The method of claim 1, wherein the forming comprises forming an array of upstanding rods or ridges.
 4. The method of claim 1, wherein the forming comprises: coating the surface of the substrate with a photoresist; patterning the photoresist to define the at least one upstanding rod or ridge therein; and stripping the photoresist from the surface of the substrate so as to leave the at least one rod or ridge upstanding thereon.
 5. The method of claim 1, wherein the depositing comprises at least one of atomic layer deposition (ALD), chemical vapor deposition (CVD) and/or or sputtering.
 6. The method of claim 1, wherein the coating comprises depositing a vapor phase of a polymer or forming a self-assembled monolayer (SAM).
 7. The method of claim 1, wherein the substrate includes a cavity, the surface of the substrate comprises a floor of the cavity, and the at least one upstanding rod or ridge is disposed at least partially within the cavity.
 8. A capacitor, comprising: a substrate; an array of upstanding rods or ridges disposed on a surface of the substrate; and a sandwich disposed over the surface of the substrate and the array of upstanding rods or ridges, the sandwich comprising at least one layer of a dielectric sandwiched between at least two electroconductive layers.
 9. The capacitor of claim 8, wherein the substrate comprises a semiconductor, glass, ceramic, an interposer or a polymer.
 10. The capacitor of claim 8, wherein at least one of the rods or ridges of the array comprises a photoresist.
 11. The capacitor of claim 10, wherein the photoresist comprises Benzocyclobutene (BCB), polyimide, spun-on glass, or SU-8.
 12. The capacitor of claim 8, wherein the at least one dielectric layer comprises Parylene or a self-assembled monolayer (SAM) comprising at least one thiol group.
 13. The capacitor of claim 12, wherein the SAM comprises an alkanethiol.
 14. The capacitor of claim 8, wherein the at least one dielectric layer comprises hafnium oxide (HfO₂), tantalum pentoxide (Ta₂O₅), zirconium dioxide (ZrO₂), yttrium oxide (Y₂O₃), lanthanum oxide (La₂O₃), titanium dioxide (TiO₂), strontium titanate (SrTiO₃), or an alkanethiol having a thiol group on both ends.
 15. The method of claim 14, wherein the alkanethiol comprises Dithiothreitol (C4H10S2), 1,2-Ethanedithiol (C2H4(SH)2), Biphenyl-4,4′-dithiol (HSC6H4SH), or 1,4-Benzenedimethanethiol (C6H4(CH2SH)2).
 16. The capacitor of claim 8, wherein at least one of the at least two electroconductive layers comprises Tantalum (Ta), Copper (Cu), Titanium (Ti), Titanium Nitride (TiN), Silver (Ag), Gold (Au), or Palladium (Pd). 